Field of the Invention
The invention relates to a semiconductor device, and more particularly to a semiconductor structure of a semiconductor device.
Description of the Related Art
In the design process for an IC chip, various clock trees are inserted into the circuit design of the IC chip, and their physical placement is adjusted accordingly. Clock adjustment is then performed on the circuit. In the process of designing and inserting the clock tree, it is important to consider the issue of clock skew. All sequential logic units (e.g. registers and latches) of the circuit need a clock signal. However, the time of the clock signal arriving at different sequential logic units is different because the path from the clock source to each sequential logic unit is different. This time difference is also called clock skew. There are various factors leading to clock skew, including the path length difference among different units, the load number and size difference, the difference caused by OCV (on-chip variation), etc. OCV includes manufacturing technical variation, operational voltage variation, ambient temperature variation, etc.
In general, clock tree synthesis (CTS) is performed to insert buffers to reduce timing skew and to construct a clock tree to reach an optimized solution by taking timing skew, circuit-area, and power consumption into consideration. However, the timing skew of the clock tree varies quite obviously for different process, temperature, and voltage corners.